Nowadays, many electronic devices incorporate functionality that operates at radio frequencies, such as mobile communication devices. The implementation of such functionality in a cost-effective manner is far from trivial. It is well-known that bipolar transistors are particularly suitable for handling signals in the radio frequency (RF) domain. However, the manufacture of integrated circuits (ICs) based on silicon bipolar transistor technology is more costly than for instance complementary metal oxide semiconductor (CMOS) ICs, and the downscaling of the device feature size is more easily achieved in CMOS technology. The cost-effective nature of CMOS technology has led to the acceptance of CMOS technology as the mainstream technology of choice for the manufacture of a wide variety of semiconductor components including ICs.
However, the breakdown characteristics of CMOS transistors limit the usefulness of CMOS transistors in RF applications unless costly measures are implemented in the CMOS process to improve these characteristics. Such costly measures typically prohibit the use of RF-CMOS technologies for manufacturing small volume devices such as analog mixed signal (AMS) devices. For these reasons, efforts have been made to produce bipolar transistors using a CMOS process flow, thereby providing mixed technology ICs in which bipolar transistors can be used for handling RF signals. An example of such an IC is provided in WO2010/066630 A1.
The challenge that process developers face is that the number of alterations to the CMOS process should remain small whilst at the same time yielding good quality bipolar transistors that are capable of handling high frequency signals. An example of a low-complexity IC including a heterojunction bipolar transistor formed in a CMOS process flow can for instance be found in WO 2003/100845 A1.
An example of such a bipolar transistor is shown in FIG. 1, and comprises a silicon substrate 10 including an active region 11 in which the collector of the bipolar transistor is formed, e.g. by provision of a buried layer in the substrate 10 or by implantation of an impurity into the substrate 10. The active region 11 is defined in between isolation regions 12, e.g. shallow trench isolation (STI) regions. The bipolar transistor further comprises a layer stack including an epitaxially grown base layer, which grows as a monocrystalline region 14 over the silicon substrate 10 and as a polycrystalline region 14′ over the isolation regions 12. A nitride layer (not shown) may be present on the isolation regions 12 to promote epitaxial growth of the base layer portion 14′.
A polysilicon base contact layer 16 is present on the base layer, which is covered by an electrically insulating layer 18. An emitter window 28 is defined over the active region 11, in which an emitter material 24 is formed, e.g. As-doped polysilicon, which is electrically insulated from the base contact layer 16 by sidewall spacers 22 in the emitter window 28 and by the electrically insulating layer 18 for the emitter material 24 deposited outside the emitter window 28, e.g. the emitter contact. The emitter material 24 is electrically insulated from the intrinsic base region 14 by further electrically insulation portions 20, which are typically formed as an etch protection layer to protect the epitaxial base layer during the opening of the emitter window. The outdiffusion 26 of the emitter 24 is surrounded by these portions 20.
The resistance between the intrinsic base portion 14 on the one hand and the extrinsic base portion 14′ and polysilicon base contact 16 on the other hand, known as the base-link resistance, is a key contributor to the total base resistance. The reduction of this resistance is a desirable goal as it leads to improved noise and frequency characteristics. It is known that the base-link resistance may be reduced by the lateral downscaling of the sidewall spacers 22 or the tuning of the lateral dimensions of the etch protection layer portions 20. However, as sidewall spacers 22 are already at a minimal thickness in most process technologies, further lateral size reductions are difficult to achieve such that it appears more promising to attempt to reduce the impact of the etch protection layer portions 20 on the base-link resistance.
U.S. patent application 2001/0053584 discloses a method of manufacturing a semiconductor device with a bipolar transistor, in which, on a monocrystalline substrate having STI regions (Shallow Trench Isolation), a number of semiconductor layers are deposited epitaxially for the formation of a base region of the transistor. On top of these semiconductor layers an etch stop layer is deposited covered by a poly crystalline silicon layer and a dielectric layer. An opening is made in these covering layers to form the emitter region. When the etch stop layer is reached, the portion of the etch stop layer covering the opening and adjoining portions of the etch stop layer are removed by means of etching.
A semiconductor layer of silicon and germanium is subsequently deposited uniformly and the hollow obtained from the under etching of the etch stop layer is completely filled up. The SiGe layer on the monocrystalline silicon surface adjoining the opening and in the adjacent hollow underneath the poly crystalline layer has a high-crystalline nature, but the layer has a low-crystalline nature elsewhere. The portion of this SiGe layer adjoining the opening is then removed by selective etching relative to the silicon lying underneath. After this the emitter region is formed by means of the opening. A drawback of the known method is that the RF properties of the devices obtained in this matter are unsatisfactory.
WO 2008/001249 A1 discloses an improvement over this method in that following the formation of the epitaxial base layer stack an etch stop layer is formed over the part of the base layer stack on top of the collector region to protect the base layer stack from the subsequent etching steps to form the emitter window. The base contact layer is subsequently deposited and covered by a silicon nitride layer after which the emitter window is formed by an etching step stopping at the etch stop layer. The etch stop layer is subsequently removed by an anisotropic etch step that at the same time forms cavities at the bottom of the emitter window that extend into the base contact layer. These cavities are subsequently filled by a high temperature treatment at 900° C. in a H2 atmosphere, which causes the migration of some of the polysilicon forming the base contact layer into the cavities, thereby substantially filling these cavities, which reduces the base-link resistance. Alternatively, SiGe may be used for the base contact layer.
However, this approach still suffers from some drawbacks. When using polysilicon as the migratory material, a high temperature of at least 900° C. has to be used to achieve the migration into the cavities, but at such temperatures diffusion of (vertical) doping profiles such as the npn doping profile cannot be avoided, which negatively affects the cut-off frequency fT of the transistor due to the increase in the major carrier delay times caused by the diffusion of these doping profiles. Alternatively, when using SiGe as the migratory material, the migration can be achieved at lower temperatures, i.e. around 800° C., but as demonstrated in FIG. 2, which depicts a bipolar transistor having a SiGe base contact layer 16 subjected to such a thermal treatment, the smoothness of the sidewalls of the emitter window 28 is negatively affected, which complicates the further processing of the bipolar transistor, thus causing both yield and transistor performance issues.